Neuronova SDK — Early Access

This is an early-access release of the Neuronova SDK, designed to give you hands-on access to a new computing paradigm: always-on, ultra-low-power analog AI at the edge.

Some features may be incomplete, APIs may evolve, and parts of the experience will change as the technology matures. This is expected at this stage.

We’re releasing the SDK early on purpose. We believe the fastest way to build the right platform is to build it together with the people who are pushing real application to the real world, not in isolation.

Your feedback is extremely important to us. What works, what doesn’t, what feels missing, all of it directly influences our roadmap, our tooling, and the next iterations of both software and silicon.

This is not just about testing an SDK.
It’s about shaping a new always-on intelligence layer at the edge.

Thank for being with us!

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Neuronova H1 version 2 Chip Overview

This section introduces the H1v2 architecture from a user perspective: how the chip is organized, why some design choices differ from H1v1, and what those choices mean when building deployable models.

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Design Direction

Second version of H1 keeps the same hardware-software philosophy of the first version, but with a different optimization target. Instead of maximizing the total number of neurons, H1v2 focuses on compact area usage, stable training behavior, more powerful neurons and practical classification readout strategies (for example population coding on the last stage).

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Layer Topology

Filter Bank Frontend

As in H1v1, signal conditioning starts with a fixed frontend made of 16 filters:

• Each filter maps one-to-one to the first neural stage
• No fan-in/fan-out is present at this frontend interface

In software, this is represented as a synapse with a diagonal 16x16 matrix.

See: reference/models for the frontend software abstraction.

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Neural Cores

After the frontend, H1v2 is organized in 3 cores:

• Core 1: 50 neurons
• Core 2: 50 neurons
• Core 3: 100 neurons
• Total: 200 neurons

Compared with H1v1, H1v2 allocates fewer neurons overall but reserves a larger final stage. This layout reflects a common SNN pattern where deep stacks do not always deliver proportional accuracy gains, while a richer output population can improve class separation and robustness.

Each core supports:

• Fully connected feedforward paths (both intra-core and inter-core)
• Optional recurrent connections that are all-to-all within the same core

Note

Core sizes do not force a strict "one layer per core" design. A logical layer can still be split across cores when needed by the mapping strategy.

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Neuron Model (High-level)

H1v2 neurons preserve hardware-driven constraints typical of analog neuromorphic systems:

• A single global firing threshold is used across the network
• The threshold is not configurable per layer or per neuron
• Membrane potential is non-negative (negative values are clipped)

The key behavioral difference from H1v1 is the post-spike update:

• H1v1 uses reset-to-zero behavior
• H1v2 uses a subtractive reset, so residual membrane information is retained after a spike

In practice, this can improve temporal memory in spiking dynamics without introducing per-neuron programmable reset rules.

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Non-Idealities (Overview)

H1v2 still includes analog variability, but its profile differs from H1v1:

• Synaptic mismatch impact is mitigated through hardware remapping techniques

• Residual non-idealities are mainly associated with:

  • Small per-neuron threshold variability
  • Leak current (time constant) mismatch and quantization

These effects can be modeled in NWAVE during training and validation. The next section details practical constraints and recommended strategies.