Hardware Constraints and Non-Idealities

This section explains how H1v2 differs from an ideal software network, which constraints are important during training, and how NWAVE models those effects before deployment.

Weight Constraints

H1v2 synaptic weights are bounded by hardware programmability:

\[ w \in [-1.66, 1.66] \]

Values outside this interval are not reliably deployable. In practice, teams usually enforce this bound through:

Direct regularization during training (see hardware losses)
Parameterized schedules that start soft and progressively harden constraints (see scheduler reference)

Sign Topology Constraint

As in H1v1, H1v2 uses a block-structured sign topology:

Neurons are grouped in blocks of 5
Incoming weights inside a block should share the same sign
Mixed-sign fan-in is penalized

Hardware-imposed sign topology (groups of 5 neurons)

This can be enforced with topology-aware losses and/or weight parameterization strategies with schedulers.

Sign Weight Magnitude Topology Scheduler

Hardware Non-Idealities

Synaptic Mismatch

The main H1v2 improvement over version 1 is at the synapse level. Hardware remapping significantly mitigates synaptic mismatch, so most H1v2 training pipelines can converge reliably without explicitly injecting synaptic mismatch noise.

This typically makes optimization more stable and shortens convergence time compared with first version of H1 mismatch-aware training.

Leak (Tau) and Threshold Variability

H1v2 still exhibits analog variability in:

Leak current (which affects effective membrane time constants)
Small per-neuron threshold variations

In NWAVE, these effects are modeled through mismatch-enabled H1v2 layers.

Example: Modeling H1v2 Variability

from nwavesdk.layers import H1v2Layer

layer = H1v2Layer(
    n_neurons=100,
    taus=20e-3,
    dt=1e-3,
    ileak_mismatch=True
)

Quantization Constraints

H1v2 deployment does not require full 32-bit floating-point precision. Weights can be quantized during training/inference to improve deployment speed and reliability.

Example: Quantized Synapse

from nwavesdk.layers import H1v2Synapse

syn = H1v2Synapse(
    nb_inputs=64,
    nb_outputs=64,
    quantization_bit=7
)

Example: Quantized Recurrent Layer

from nwavesdk.layers import H1v2Layer

layer = H1v2Layer(
    n_neurons=100,
    taus=20e-3,
    dt=1e-3,
    layer_topology="RC",
    quantization_bit=7
)

Quantization remains a soft constraint: higher precision is possible, but generally requires more manual effort during hardware programming and calibration.

Summary

H1v2 enforces structural and numerical constraints required by hardware deployment
The same sign-topology logic of the first version of the chip still applies, with H1v2-specific scheduling options
Synaptic mismatch is largely mitigated in H1v2, while leak/threshold variability remains relevant
Quantization (typically 6 to 7 bits) is recommended for practical deployment workflows