Neuronova SDK — Early Access

This is an early-access release of the Neuronova SDK, designed to give you hands-on access to a new computing paradigm: always-on, ultra-low-power analog AI at the edge.

Some features may be incomplete, APIs may evolve, and parts of the experience will change as the technology matures. This is expected at this stage.

We’re releasing the SDK early on purpose. We believe the fastest way to build the right platform is to build it together with the people who are pushing real application to the real world, not in isolation.

Your feedback is extremely important to us. What works, what doesn’t, what feels missing, all of it directly influences our roadmap, our tooling, and the next iterations of both software and silicon.

This is not just about testing an SDK.
It’s about shaping a new always-on intelligence layer at the edge.

Thank for being with us!

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Neuronova H1-version 1 Chip Overview

This section provides a high-level description of the Neuronova neuromorphic chip architecture. The goal is to give users enough context to understand how networks are mapped to hardware, without going into circuit-level details.

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Deprecation alert

This was the first architecture developed at Neuronova and was initially used only internally. The evaluation kit will include the second version of H1. However, support for the first architecture is retained in later releases to allow teams who previously developed networks on it to continue using them as references and ensure backward compatibility. This architecture is planned to be deprecated and will not be supported in the future.

Layer Topology

The chip implements a fixed hierarchical topology:

Filter Bank Frontend

• The frontend consists of 16 filters
• Each filter output is mapped one-to-one to a neuron in the first neural layer
• There is no fan-in or fan-out at this stage

In software, this is modeled as a synapse with a diagonal 16×16 weight matrix. This abstraction is provided in the frontend reference implementation.

See: reference/models for the software mapping of the filter bank.

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Neural Cores

After the frontend, the chip contains:

• 4 cores
• 64 neurons per core
• Total neurons: 256

Each core supports:

• Fully connected feedforward connections (intra- and inter-core)
• Optional recurrent connections, which are:
• All-to-all
• Restricted to neurons within the same core

Note

This doesn't constrain that each layer has to be composed of less than 64 neurons, since layer's neurons can be split across cores.

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Neuron Model (High-level)

The neuron model differs from ideal software neurons in a few key aspects:

• A single fixed firing threshold is used across the entire network
• The threshold value cannot be changed per layer or per neuron
• Membrane potential is strictly non-negative
• Negative voltages are clipped by design
• Reset is to zero and can't be changed

These constraints reflect the physical implementation of the neuron circuits on chip.

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Non-Idealities (Overview)

The chip exhibits non-idealities typical of analog neuromorphic hardware, including:

• Synaptic weight mismatch
• Leak current (time constant) mismatch

These effects can be explicitly modeled in software using the NWAVE library. The next section describes these constraints in more detail and how to account for them.